1. Field of the Invention
The invention generally relates to a method used in semiconductor manufacturing and, more particularly, to a phase-locked loop (PLL) method used to synchronize circuit timing in the fabrication of integrated circuits (ICs).
2. Description of Prior Art
Because sequential data may vary in both frequency and phase, phase-locked loops with both frequency and phase locking are typically used to sample that data. The design of these systems is complex and the circuits consume substantial power. One application where this is utilized is in the transfer of data to a display in a portable computer. Here, especially, the excessive power dissipation is undesirable.
Refer now to FIG. 1 showing a typical PLL system for generating an internal synchronization clock (CLKOUT). The reference clock (CLKIN) is applied to the input of a variable delay circuit 10 and the input of a phase comparator 12. The output, CLKOUT, of the variable delay circuit 10 is applied to a second input of the phase comparator 12. The phase comparator 12 output, PCOUT, is an error signal that indicates whether the rising edge of CLKOUT leads or lags CLKIN. PCOUT is then applied to the variable delay circuit 10 to either advance or retard CLKOUT in order to maintain the proper phase relationship. One problem with this circuit is the complexity of the phase comparator and variable delay circuit. The variable delay circuit is typically composed of a plurality of series connected inverter pairs where phase and frequency are changed by adding or removing inverter pairs. Another problem is that the circuit corrects the phase relationship even when the phase difference is small. This results in output jitter and substantial power dissipation during the correction cycle. Finally, this method is poor for applications requiring a wide frequency range and where the frequency of CLKOUT is N times that of CLKIN.
Other approaches related to improving PLL circuits exist. U.S. Pat. No. 6,157,690 to Yoneda teaches a method where a PLL phase correction circuit has three modes of operation. When the phase difference between the input and output clock are within a first minimum range, no phase correction is performed. When the phase difference between the input and output clocks exceed the first minimum range, but fall within a second larger range, a slow correction method that consumes a low level of power is employed. When the phase difference exceeds the second range, a faster method using more power is used. U.S. Pat. No. 5,694,068 to Rokugo teaches a method where the input and output frequencies are each applied to frequency dividers. The frequency dividers generate multiple phases of the divided signal, which are applied to a plurality of quantized phase comparators. The output of the quantized comparators are added and when the sum reaches a certain upper (or lower) limit, a pulse is decremented (or added) to a pulse train which is later divided to create the output frequency. U.S. Pat. No. 5,923,715 to Ono teaches a method where both frequency and phase differences are used to control the PLL signal output. A variable delay circuit with both inverters and capacitors to adjust phase is used. U.S. Pat. No. 6,384,650 B1 to Fukunaga et al. teaches a method using an additional control loop with an adder and differentiator to calculate the frequency difference between the fixed oscillator and PLL output, memory to store that difference, and another circuit to compare the current frequency difference with the previously memorized difference. The result from this additional control loop contributes to the voltage controlled output oscillator frequency. U.S. Pat. No. 6,389,091 B1 to Yamaguchi et al. teaches a method of PLL where the variable controlled oscillator (VCO) frequency is varied by connecting and disconnecting paralleled transistors in a loop containing an odd number of inverters. Using this method, more precise control of the frequency may be made thereby minimizing jitter.